Liquid crystal display devices (LCDs) characterized by their thin design, light weight and low power consumption have come into widespread use in recent years and are utilized in the display units of mobile devices such as portable telephones (mobile telephones or cellular telephones), PDAs (Personal Digital Assistants) and laptop personal computers. Recently, however, liquid crystal display devices have come to be provided with large-size screens and techniques for dealing with moving pictures have become more advanced, thus making it possible to realize not only mobile applications but also stay-at-home large-screen display devices and large-screen liquid crystal televisions. Liquid crystal display devices that rely upon active matrix drive and are capable of presenting a high-definition display are being utilized as these liquid crystal displays devices.
The typical structure of an active-matrix liquid crystal display device will be described with reference to FIG. 11. The principal components connected to one pixel of a liquid crystal display unit are illustrated schematically by equivalent circuits in FIG. 11.
In general, a display unit 960 of an active-matrix liquid crystal display device comprises a semiconductor substrate on which transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 are laid out in the form of a matrix (e.g., 1280×3 pixel columns×1024 pixels rows in the case of a color SXGA panel); an opposing substrate on the entire surface of which a single transparent electrode 967 is formed; and a liquid crystal material sealed between these two substrates arranged to oppose each other. The liquid crystal has capacitance and forms a capacitor 965 between the pixel electrodes 964 and electrode 967. Further, an auxiliary capacitor 966 for assisting the capacitance of the liquid crystal is provided.
In the above-described liquid crystal display device, the TFT 963, which has a switching function, is turned on and off under the control of a scan signal. When the TFT 963 is on, a grayscale signal voltage that corresponds to a video data signal is applied to the pixel electrode 964, and the transmittance of the liquid crystal changes owing to a potential difference between each pixel electrode 964 and opposing-substrate electrode 967. This potential difference is held by the liquid crystal capacitance 965 and auxiliary capacitor 966 for a fixed period of time even after the TFT 963 is turned off, as a result of which an image is displayed.
Data lines 962 that send a plurality of level voltages (grayscale signal voltages) applied to pixel electrodes 964 and scan lines 961 that send the scan signal are wired on the semiconductor substrate in the form of a grid (the data lines are 1280×3 in number and the scan lines are 1024 in number in the case of the above-mentioned color SXGA panel). The scan line 961 and data line 962 constitute a large capacitive load owing to the capacitance produced at the intersection of these lines and capacitance, etc., of the liquid crystal sandwiched between the opposing-substrate electrodes.
It should be noted that the scan signal is supplied to the scan line 961 by a gate driver 970, and that the supply of grayscale signal voltage to each pixel electrode 964 is performed by a data driver 980 via the data line 962. Further, the gate driver 970 and data driver 980 are controlled by a display controller (not shown), a required clock CLK, control signals and power-supply voltage, etc., are supplied from the display controller, and video data is supplied from the display controller 940 to the data driver 980. At the present time, video is principally digital data.
Rewriting of one screen of data is carried out over one frame ( 1/60 of a second), data is selected successively every pixel row (every line) by each scan line, and a grayscale signal voltage is supplied from each data line within the selection interval.
Although the gate driver 970 need only supply at least a bi-level  scan signal, it is required that the data driver 980 drive the data lines by grayscale signal voltages of multiple levels that conform to the number of gray levels of the grayscale. To this end, the data driver 980 has a digital-to-analog converter (DAC) comprising a decoder for converting video data to a grayscale signal voltage and an operational amplifier for amplifying the grayscale signal voltage and outputting the amplified signal to the data line 962.
With the progress that has been made in raising image quality (increasing the number of colors) in liquid crystal display devices, there is now growing demand for video data of at least six bits per each of R, G, B (260,000 colors) and even eight bits or more per each of R, G, B (26,800,000 colors). For this reason, a data driver that outputs a grayscale signal voltage corresponding to multiple-bit video data is required to provide a highly accurate output voltage along with a multiple-level grayscale voltage output. For example, if the allowable output voltage accuracy is ½ LSB (Least Significant Bit), we will have approximately ±40 mV in case of six bits and approximately ±10 mV in case of eight bits.
However, the transistors that constitute the driver circuit exhibit a variation in characteristics owing to the fabrication process and hence there is a limit upon the improvement in accuracy of the output voltage. A method of raising the accuracy of output voltage effectively in view of this problem has been proposed in Patent Document 1, cited below.
FIGS. 12A and 12B are diagrams illustrating the circuit configuration of an operational amplifier disclosed in Patent Document 1. This is applied to the driving of a liquid crystal display device. FIGS. 12A and 12B show two connection configurations that depend upon the changeover of switches in one operational amplifier. As shown in FIGS. 12A and 12B, the operational amplifier includes two P-channel MOS transistors (referred to as “PMOS transistors”) MP91, MP92 that construct a differential pair; a constant current source I91; N-channel MOS transistors (referred to as “NMOS transistors”) MN91, MN92 that construct a current mirror circuit; an NMOS transistor MN93; a constant current source I92; a phase compensating capacitor C91; break-type switches S1, S4, S6, S8 and make-type switches S2, S3, S5, S7.
The drain of one PMOS transistor MP91 constituting the differential pair is connected to the drain of the NMOS transistor MN91. Further, the drain of the other PMOS transistor MP92 constituting the differential pair is connected to the drain of the NMOS transistor MN92.
The constant current source I91, which is inserted between the coupled sources of the PMOS transistors MP91 and MP92 constituting the differential pair and a positive power supply (power supply on the high potential side), biases (supplies a current to) the differential pair. The NMOS transistors MN91 and MN92 constituting the current mirror function as a active load of the differential pair and convert the input differential signal to a single-ended signal.
The NMOS transistor MN93 composes an amplifying circuit of a second stage (output stage). The constant current source I92, which is inserted between the positive power supply VDD and the drain of the NMOS transistor MN93, acts as the active load of the NMOS transistor MN93. The phase compensating capacitor C91 is connected between the gate and drain of the NMOS transistor MN93.
The break-type switch S1 is connected between the gate and drain of NMOS transistor MN91, the make-type switch S2 is connected between the gate and drain of NMOS transistor MN92, the make-type switch S3 is connected between the drain of NMOS transistor MN91 and the gate of NMOS transistor MN93, the break-type switch S4 is connected between drain of NMOS transistor MN92 and the gate of NMOS transistor MN93, the make-type switch S5 is connected between the gate of PMOS transistor MP92 and output terminal Vout, the break-type switch S6 is connected between the gate of PMOS transistor MP91 and output terminal Vout, the make-type switch S7 is connected between the gate of PMOS transistor MP91 and input terminal Vin, and the break-type switch S8 is connected between the gate of PMOS transistor MP92 and input terminal Vin.
The switches S1 to S8 are all gang-controlled and are changed over between odd- and even-numbered frames, by way of example. FIG. 12A illustrates the state of the switch connections at the time of an odd-numbered frame, and FIG. 12B illustrates the state of the switch connections at the time of an even-numbered frame.
When switch S1 is closed in this operational amplifier, as illustrated in FIG. 12A, the drain of NMOS transistor MN92 delivers a single-end output. When switch S2 is closed, as illustrated in FIG. 12B, the drain of the NMOS transistor MN91 delivers a single-end output.
Thus, since the node of the single-end output changes back and forth depending upon the states of switches S1 and S2, the switches S3 and S4 select the output node. The single-end-converted signal selected via the switches S3 and S4 is input to the gate of NMOS transistor MN93, which is the output transistor. At this time the constant current source I92 acts as the active load of the NMOS transistor 93. The drain of NMOS transistor MN93 becomes the output terminal Vout. The phase compensating capacitor C91 performs phase compensation as a mirror capacitor.
Since this operational amplifier is used as a buffer amplifier, the inverting input terminal and output terminal thereof are coupled together in a so-called voltage-follower connection.
By changing over the switches S5 to S8, the inverting input terminal becomes the gate of PMOS transistor MP91 or the gate of PMOS transistor MP92.
In the state of the connections shown in FIG. 12A, the switches S1, S4, S6 and S8 are turned on, the gate of PMOS transistor MP91 is connected to the output terminal Vout as the inverting input terminal, and the gate of PMOS transistor MP92 is connected to the input terminal Vin as the non-inverting input terminal, whereby a voltage-follower connection is obtained.
In the state of the connections shown in FIG. 12B, on the other hand, the switches S2, S3, S5 and S7 are turned on, the gate of PMOS transistor MP91 is connected to the input terminal Vin as the non-inverting input terminal, and the gate of PMOS transistor MP92 is connected to the output terminal Vout as the inverting input terminal, whereby a voltage-follower connection is obtained.
Thus, as a result of changing over the switches S1 to S8, two states of connection exist and the two states of connection are changed over at a prescribed period.
In the state of the switch connections shown in FIG. 12A, assume that an offset voltage (+Vos) is produced.
In this case, if the switches S1 to S8 are changed over from the state of the switch connections of FIG. 12A to obtain the state of the switch connections shown in FIG. 12B, then the offset voltage will be −Vos.
If this operational amplifier is used to drive a liquid crystal display device, voltage is converted to luminance. If an offset voltage is produced, therefore, the luminance will vary. However, there is a limitation upon the resolving power of the human eye in terms of recognizing a change in luminance. If luminance varies in excess of a prescribed period, therefore, the average of this luminance will be recognized.
Accordingly, in an operational amplifier used in driving a liquid crystal display device, offset voltage is averaged effectively, i.e., nulled, by changing over the switches S1 to S8 at the prescribed period or greater.
FIG. 13 is a diagram illustrating the circuit arrangement of a typical amplifier disclosed in Patent Document 2, which is cited below. As shown in FIG. 13, the arrangement is not one in which offset is cancelled by changing over switches as in the amplifier described above with reference to FIGS. 12A and 12B. However, this amplifier will be described for the purpose of comparison with the present invention.
As shown in FIG. 13, the amplifier can be considered upon being divided into an input stage 810, intermediate stage 820 and final stage 830.
The input stage 810 includes PMOS transistors MP80, MP81, MP82 and NMOS transistors MN80, NMN81, MN82.
The intermediate stage 820 includes PMOS transistors MP83, MP84, MP85, MP86, MP87 and MP88 and NMOS transistors MN83, NMN84, MN85, MN86, MN87 and MN88.
The final stage 830 includes a PMOS transistor MP89 and an NMOS transistor MN89.
The amplifier further includes phase compensating capacitors C81, C82 between the intermediate stage 820 and the final stage 830.
The PMOS transistors MP81 and MP82 have their sources coupled together and construct a P-channel differential pair. The PMOS transistor MP80 is connected between this P-channel differential pair and a positive power supply (power supply on the high potential side) VDD. The PMOS transistor MP80 has a source connected to the positive power supply VDD, a drain connected to the coupled sources of PMOS transistors MP81, MP82 and a gate connected to a constant voltage source terminal BP81. The PMOS transistor MP80 acts as a constant current source.
The NMOS transistors MN81 and MN82 have their sources coupled together and construct an N-channel differential pair. The NMOS transistor MN80 is connected between this N-channel differential pair and a negative power supply (power supply on the low potential side) VSS. The NMOS transistor MN80 has a source connected to the negative power supply VSS, a drain connected to the coupled sources of NMOS transistors MN81, MN82 and a gate connected to a constant voltage source terminal BN81. The NMOS transistor MN80 acts as a constant current source.
The gate of PMOS transistor MP81 and the gate of NMOS transistor MN81 are connected in common with an input terminal INN. The gate of the PMOS transistor MP82 and the gate of the NMOS transistor MN82 are connected in common with an input terminal INP.
The drain of the PMOS transistor MP81 is connected to a node C of connection between the drain of the NMOS transistor MN83 and the source of the NMOS transistor MN85 in the intermediate stage 820.
The drain of PMOS transistor MP82 is connected to a node D of connection between the drain of NMOS transistor MN84 and the source of NMOS transistor MN86.
The drain of NMOS transistor MN81 is connected to a node A of connection between the drain of PMOS transistor MP83 and the source of PMOS transistor MP85.
The drain of NMOS transistor MN82 is connected to a node B of connection between the drain of PMOS transistor MP84 and the source of PMOS transistor MP86.
The PMOS transistors MP83, MP84 have their sources coupled together and their gates coupled together, and the coupled sources are connected to the positive power supply VDD. The drains of the PMOS transistors MP83, MP84 are connected to the nodes A and B, respectively.
The PMOS transistor MP85 has its source connected to the node A and its drain connected to the coupled gates of the PMOS transistors MP83, MP84, the source of the PMOS transistor MP87 and the drain of the NMOS transistor MN87.
The PMOS transistor MP86 has its source connected to the node B and its drain to the source of PMOS transistor MP88, the drain of NMOS transistor MN88 and the gate of the PMOS transistor MP89.
The gates of the PMOS transistors MP85, MP86 are coupled together and connected to a constant voltage source terminal BP82.
The NMOS transistors MN83, MN84 have their sources coupled together and their gates coupled together, and the coupled sources are connected to the negative power supply VSS.
The drains of the NMOS transistors MN83, MN84 are connected to the nodes C and D, respectively.
The NMOS transistor MN85 has its source connected to the node C and its drain connected to the coupled gates of the NMOS transistors MN83, MN84, the source of the NMOS transistor MN87 and the drain of the PMOS transistor MP87.
The NMOS transistor MN86 has its source connected to the node D and its drain connected to the source of the NMOS transistor MN88, the drain of the PMOS transistor MP88 and the gate of the NMOS transistor MN89. The gates of the NMOS transistors MN85, MN86 are coupled together and connected to a constant voltage source terminal BN82.
The PMOS transistor MP87 has its gate connected to a constant voltage source terminal BP83, its source connected to the drain of PMOS transistor MP85 and its drain connected to the drain of NMOS transistor MN85.
The NMOS transistor MN87 has its gate connected to a constant voltage source terminal BN83, its source connected to the drain of NMOS transistor MN85 and its drain connected to the drain of PMOS transistor MP85.
The PMOS transistor MP87 and NMOS transistor MN87 act as floating current sources.
The PMOS transistor MP88 has its gate connected to a constant voltage source terminal BP84, its source connected to the drain of PMOS transistor MP86 and its drain connected to the drain of NMOS transistor MN86.
The NMOS transistor MN88 has its gate connected to a constant voltage source terminal BN84, its source connected to the drain of the NMOS transistor MN86 and its drain connected to the drain of the PMOS transistor MP86.
The PMOS transistor MP88 and NMOS transistor MN88 act as floating current sources.
The PMOS transistor MP89 has a source connected to the positive power supply VDD, a gate connected to the source of the PMOS transistor MP88 and a drain connected to the output terminal OUT. This is an output transistor.
The NMOS transistor MN89 has a source connected to the negative power supply VSS, a gate connected to the source of the PMOS transistor MN88 and a drain connected to the output terminal OUT. This is an output transistor.
The phase compensating capacitor C81 has a first end connected to the node B and a second terminal connected to the output terminal OUT. The phase compensating capacitor C82 has a first end connected to the node D and a second terminal connected to the output terminal OUT.
The differential amplifier illustrated in FIG. 13 is a so-called “rail-to-rail amplifier” (a full-range amplifier). The input stage 810 is a differential stage obtained by bundling the PMOS-transistor differential pair and the NMOS-transistor differential pair in order to implement the rail-to-rail capability. Accordingly, it is necessary to couple the outputs of the PMOS-transistor differential pair and the outputs of the NMOS-transistor differential pair.
The outputs of the differential stage, therefore, are connected to the nodes A, B and C, D of so-called folded-cascode connections.
By virtue of this connection, the outputs of the PMOS-transistor differential pair and NMOS-transistor differential pair are coupled in terms of current.
The NMOS-transistor differential pair operates within an input-signal voltage range in which the PMOS-transistor differential pair does not operate. Conversely, the PMOS-transistor differential pair operates within an input-signal voltage range in which the NMOS-transistor differential pair does not operate. As a result, it is possible to obtain an input stage that operates in the full input range of power supply voltages (VDD to VSS).
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-11-249623 (FIG. 14)
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A-6-326529 (FIG. 1)
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-P2001-34234A (FIG. 5)
[Patent Document 4]
Japanese Patent Kokai Publication No. JP-P2002-43944A (FIGS. 2 and 3)
[Patent Document 5]
Japanese Patent Kokai Publication No. JP-P2005-130332A (FIGS. 1 and 26)